Speculative instructions exection in VLIW processors

摘要

The object of the present invention is to improve the execution of instructions using speculative operations in Superscalar or Very Long Instruction Word (VLIW) processors having multiple Arithmetic Logic Units (ALUs). More particularly, the invention relates to a system and method for using standard registers as shadow registers. The addresses of all standard registers are translated using a Relocation Table (RT) array. The addresses of registers used as shadow registers are translated another time using a Speculative Registers Table (SRT) array. At branch completion time, for the speculative operations that have previously been executed and correctly predicted, the Relocation Table (RT) is updated with the Speculative Registers Table (SRT) content. For the speculative operations that have previously been executed and incorrectly predicted, the Relocation Table (RT) remains unchanged. The present invention performs the same function as processors using state of the art hardware shadow registers while using a limited number of read/write ports standard register array.