发明名称 |
Apparatus for determining the instantaneous average number of instructions processed |
摘要 |
An apparatus is provided for determining an average number of instructions entering a stage of a processor pipeline of a computer system during a clock cycle of a processor clock. The number of instructions entering a particular stage of the pipeline are stored in a queue during each of a predetermined number (N) of clock cycles. The total number of instructions processed over the last P clock cycles is computed, where P is less than or equal to N. The total number of instructions processed is divided by the last P processor cycles to yield the instantaneous average number of instructions processed for each processor cycle. This average number of instructions processed is communicated to software. |
申请公布号 |
US6175814(B1) |
申请公布日期 |
2001.01.16 |
申请号 |
US19970977438 |
申请日期 |
1997.11.26 |
申请人 |
COMPAQ COMPUTER CORPORATION |
发明人 |
CHRYSOS GEORGE Z.;DEAN JEFFREY;HICKS, JR. JAMES E.;WALDSPURGER CARL A.;WEIHL WILLIAM E. |
分类号 |
G06F11/34;(IPC1-7):G06F9/00 |
主分类号 |
G06F11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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