发明名称 |
Error correction apparatus and associated method utilizing parellel processing |
摘要 |
Apparatus, and an associated method, for performing error-correction operations to correct errors in a block of block-encoded data. Two ALUs are operable in parallel to perform finite-field mathematical operations and to calculate addresses used pursuant to the error-correction calculations. Instructions pursuant to which the ALUs are operable are stored in a memory device. The instructions are retrieved during operation of error-correcting calculations. The manner by which the error-correcting apparatus operates is alterable by appropriate alteration of the instructions stored at the memory device.
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申请公布号 |
US6175941(B1) |
申请公布日期 |
2001.01.16 |
申请号 |
US19980207349 |
申请日期 |
1998.12.08 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
POEPPELMAN ALAN D.;RUTHERFORD MARK D. |
分类号 |
H03M13/00;H03M13/47;(IPC1-7):H03M13/00;G06F15/00 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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