| 摘要 |
PURPOSE: A delay locked circuit is provided to have a power save function without a limitation for a high-speed operation and a times by compensating for a loss capacitor value upon a transition from a power save mode to a normal operation mode. CONSTITUTION: The first and second store device each store a low pulse width and a high pulse width of a clock feedbacked from the outputs thereof as a voltage level. The first and second voltage applying device compensates for a loss capacitor value with a predetermined value by supplying the first and second power supply voltage to the first and second store device. A transmitting device is connected to the first and second store device. A control device controls the operation of the first and second voltage applying device and the transmitting device on the basis of a power save mode and nap mode.
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