| 摘要 |
PURPOSE: An apparatus for building a memory therein is provided to shift one-bit internal test data to generate n-bit internal test data so as to reduce circuit sizes, and to shorten a path through which data generated in a logic circuit is transmitted to a memory, so as to perform a high speed operation. CONSTITUTION: A memory(108) stores data. A built-in self test(BIST) circuit generates one-bit test data. A logic circuit(100) controls write/read operations of the memory(108), and generates n-bit write data for being written in the memory(108). A data interface(110) responds to a first/a second selection signals to receive one-bit internal test data generated in the BIST circuit(102), and shifts the one-bit internal test data n times, then generates n-bit internal test data, or receives n-bit write data generated in the logic circuit(100). The data interface(110) transmits the received n-bit write data to the memory(108) or receives n-bit external test data from an exterior, then transmits the n-bit external test data to the memory(108).
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