| 摘要 |
PURPOSE: A memory device for driving a packet command is provided which controls the data output time stably and reduces the area by simplifying the logic configuration of a shift register. CONSTITUTION: The device controls the data output time directly from a shift register block by generating a domain signal using a signal generated from a register(21) in the device instead of generating a control signal to control the shift register block in an interface block. The memory device includes: the first signal generation unit(31) generating the domain signal of a fixed bits by inputting the signal generated from the register; the second and the third signal generation unit(33,34) generating the first and the second control signal for loading data; the fourth and the fifth signal generation unit(35,36) generating the third and the fourth signal to read data from a core block(20); and a data output shift block(38) which shifts data read from the core block according to the first and the second control signal and a clock signal generated from the second and the third signal generation unit, and compensates the data output time by delaying the data shifted according to the domain signal generated from the first signal generation unit according to each domain by a fixed time.
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