| 摘要 |
PURPOSE: A method for manufacturing a ferroelectric memory device is provided to reduce the number of manufacturing steps, by forming a capacitor barrier layer without an additional processes for exposure, development and cleaning. CONSTITUTION: The second interlayer dielectric is formed on the entire structure having a transistor and the first interlayer dielectric covering the transistor. The second interlayer dielectric is selectively etched to form the first contact hole exposing a plate electrode of a capacitor. A barrier layer is formed on the entire structure. The barrier layer, the second interlayer dielectric and the first interlayer dielectric are selectively etched to form the second contact hole exposing an active region of the transistor. A metal layer is formed on the entire structure. The metal layer and barrier layer are patterned to form an interconnection wherein the barrier layer and the metal layer are stacked in the first contact hole and the metal layer is stacked in the second contact hole.
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