| 摘要 |
PURPOSE: A wafer level package is provided to reduce the access time for a semiconductor chip by enlarging the distance between the semiconductor chip and a metal pattern. CONSTITUTION: A wafer level package comprises a semiconductor chip formed with bonding pad(11) at a surface thereof. At least two lower insulation layers having via holes for exposing the bonding pads(11) are coated on the surface of the semiconductor chip. A metal connecting pad is deposited on the via holes except for the via holes formed on the lower insulation layers so as to be connected to the bonding pads(11). A metal pattern(32) is connected to the metal connecting pad(30). An upper insulation layer is coated on the lower insulation layers and is provided with a ball land(27) for exposing an other end of the metal pattern(32). An adhesive auxiliary layer(40) is formed on the ball land(27). A solder ball(50) is mounted on the adhesive auxiliary layer(40).
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