| 摘要 |
PURPOSE: A wafer level package and a method for making the same are provided to prevent that a crack is formed on interfacial surface between a junction auxiliary layer and an insulating layer by maximally suppressing a side stress on the junction auxiliary layer. CONSTITUTION: A wafer level package includes a semiconductor chip having many bonding pads(11), a lower insulating layer(20), a metal pattern(30), a junction auxiliary layer(40), an upper insulating layer(61) and a solder ball(70). The lower insulating layer is deposited on the semiconductor chip in order to expose a bonding pad of the semiconductor chip. The metal pattern is connected its one end to the bonding pad, and a via hole is formed to the other end positioned on the lower insulating layer. The junction auxiliary layer is deposited on the via hole, is positioned on the same plane as the metal pattern. The bottom of the junction auxiliary layer is contacted with the lower insulating layer, a side of which is contacted with the metal pattern, and edge of which is contacted with the metal pattern surface. The upper insulating layer is deposited on a total structure in order to expose the junction auxiliary layer. The solder ball is mounted to the junction auxiliary layer.
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