| 摘要 |
A microprocessor configured to use historical scan information to speed instruction scanning is disclosed. The microprocessor may comprise an instruction cache, a scanning history table, routing logic, and two or more scanning units. The instruction cache is configured to output sequences of stored instruction bytes in response to receiving corresponding fetch addresses. The scanning history table, which may also receive the fetch addresses, is configured to output corresponding stored scan block boundary information. The routing logic, which is coupled between the instruction cache, scanning history table, and scanning units, is configured to route the first N instructions to the first scanning unit, and the second N instructions to the second scanning unit, wherein N is a predetermined integer greater than one. The scanning units are configured to operate independently and in parallel. The scanning history information may be initially stored in the scanning history table by a predecode unit coupled between the instruction cache and a memory subsystem. Alternatively, the scanning units may scan the instructions in a traditional manner during a first access and then store the scan information in the scanning history table for subsequent accesses. The scan history information may be stored in the scan history table as scan block indicator bits or as byte counts associated with a particular fetch address. A computer system and method for scanning instructions are also disclosed.
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