| 摘要 |
PURPOSE: A jitter controlling apparatus of a delay locked loop is provided which realizes a semiconductor memory device having reduced jitter by using a unit delay device reducing unit delay time and a comparator for discriminating a minute timing skew. CONSTITUTION: A delay locked loop clock generating apparatus includes a delay locked loop clock generator(110) for generating an initial delay locked loop clock through unit delay and multi-step delay and through comparison with a reference clock, a fine control comparator(130) for comparing the reference clock with the delay locked loop clock in response to a control signal to generate a comparison output signal, a controller(150) for generating first to fifth switch enable signals which determine the amount of delay in response to the comparison output signal, and a fine delay(170) for delaying the delay locked loop clock, passing it through first to fifth fine unit delay devices having delay time shorter than the unit delay time, in response to the first and fifth switch enable signals, to generate a secondary delay locked loop clock. The secondary delay locked loop clock is fed back as the delay locked loop clock signal of the fine control comparator to repeatedly perform the comparison processor, determining the amount of delay again.
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