发明名称 |
SYSTEM AND METHOD FOR MANAGING FIFO ADDRESS FOR IPC |
摘要 |
PURPOSE: A system for managing a FIFO(first in first out) address for an IPC(interprocessor) is provided to operate according to a designated cell unit by deciding the size of the cell for managing both write and read addresses of a FIFO. CONSTITUTION: A FIFO memory(10) consists of write and read addresses for indicating each byte in a single block as well as a block address for displaying each cell block. A write address control unit(20) generates a write address for recording data on the FIFO memory. A FIFO state control unit(30) shows how much data are recorded on the FIFO memory. A read address control unit(40) generates a read address used to read the data from the FIFO memory. A FIFO size selecting control unit decides the size of the FIFO memory on the basis of the size of the cell block fed from outside.
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申请公布号 |
KR20010002881(A) |
申请公布日期 |
2001.01.15 |
申请号 |
KR19990022931 |
申请日期 |
1999.06.18 |
申请人 |
SUNGWOO PRECISION & IND.CO., LTD. |
发明人 |
PARK, SUN JUN |
分类号 |
G06F12/00;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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