| 摘要 |
PURPOSE: A method for manufacturing a semiconductor memory device including a self-aligned contact process is provided to improve an electrical characteristic, by guaranteeing a sufficient contact region in a cell region without varying a layout or having an influence on a peripheral circuit region. CONSTITUTION: A gate having a mask insulating layer(23) is formed on a semiconductor substrate(20). The first etching barrier-insulating layer is formed on the resultant structure. The first etching barrier insulating layer is anisotropically etched to form the first spacer(24) on a side wall of the gate. The second etching barrier-insulating layer is formed on the resultant structure. The second etching barrier insulating layer in a peripheral circuit region is selectively and anisotropically etched to form the second spacer, wherein the first and second spacers constitute a lightly doped drain(LDD) spacer. A planarized interlayer dielectric oxide layer is formed on the resultant structure. The interlayer dielectric oxide layer in a cell region and the second etching barrier insulating layer are selectively etched to form a self-aligned contact hole.
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