| 摘要 |
PURPOSE: A ferroelectric memory device is provided which embodies a high integration by reducing an area of a device by making each ferroelectric capacitor of a number of unit cells share one switching NMOS transistor. CONSTITUTION: The device comprises: a switching transistor(252) whose gate terminal is connected to a word line and one side is connected to a bit line; and a number of ferroelectric capacitors(211,212) whose one terminal is connected to another terminal of the above switching transistor in parallel and another terminal of each switching transistor is connected a different plate line each other. Each ferroelectric capacitor of a number of unit cells shares the above switching transistor. Each plate line is connected to a global plate line in common through the corresponding switching device.
|
