| 摘要 |
PURPOSE: A circuit for generating a data switch control signal of a memory device is provided which is enabled only while data is inputted according to a burst length, and operates rapidly and accurately even when an interrupt or a write command enters continuously. CONSTITUTION: The device uses a common data bus and is constituted with modules. A circuit of the memory device generates a data switch control signal(QFCB, DQ FET Control Bar). The circuit forms a window during a timing when data is inputted/output using a counter comprising an internal shift register during a write command. The circuit includes: a number of shifting counting units shift-counting a write command signal by being controlled by a clock signal and a reset signal; a QFCB enable signal generation unit to enable the data switch control signal(QFCB) through a logic operation of each output of the shifting counting units; an output driving signal generation unit to generate a pull down driving signal and a pull up driving signal with the QFCB enable signal as an input; and an output driving unit(44) outputting the QFCB by being controlled by the pull down driving signal and the pull up driving signal.
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