| 摘要 |
PURPOSE: A synchronous DRAM is provided to prevent data access time from being delayed by a precharge interrupt path without considering a timing margin. CONSTITUTION: A synchronous DRAM includes a command decoder(20), a column decoder, a precharge interrupt portion(23), a sensing amplifier(27), the first and second switching portions, and a switching controller. The column decoder decodes a column address signal in response to a column address beginning pulse signal and an inner column address beginning pulse signal outputted from the command decoder. The precharge interrupt portion outputs a precharge interrupt signal under the control of a word line precharge beginning pulse signal and an active bank confirming signal outputted from the command decoder. The sensing amplifier senses and amplifies a bit line data. The first switching portion electrically connects the output terminal of the sensing amplifier with a local data bus under the control of the output of the column decoder. The second switching portion electrically switches the local data bus to a global data bus. The switching controller outputs the controlling signal of the second switching portion under the control of the bank active beginning pulse outputted from the command decoder and the precharge interrupt signal.
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