| 摘要 |
PURPOSE: A delay locked loop(DLL) is provided to significantly reduce initial locking time in generating an internal clock signal which matches to the phase of an external clock signal. CONSTITUTION: A DLL comprises a buffering unit for buffering an external clock signal; a delay line unit consisting of plural unit delay elements and which receives and delays the buffered external clock signal from the buffering unit, and outputs the delayed signal as an internal clock signal; a phase comparing unit for receiving the external and internal clock signals, comparing phases of the signals, and outputting first to fourth phase comparison result signals; and a control unit for performing a binary search locked type sequencing in response to the external clock signal, pre-fetch signal and the phase comparison result signals, and outputting plural delay control signals to the unit delay elements. The control unit includes a 4-bit ring counter(231) for counting in response to the external clock signal, an OR gates(240,241) for OR-ing phase comparison result signals from the phase comparator, a 4-bit register(232) for storing 4-bit counting result signals output from the ring counter, a 4x16 decoder(233) for decoding 4-bit signals from the 4-bit register, an OR gate(234) for OR-ing the 4-bit counting result signal from the ring counter, a D-flip flop(235) for outputting a wait signal, four AND gates(236-239), and a shift register(250).
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