| 摘要 |
PURPOSE: A wafer level stack package and a method for making the same are provided to make a packaging process by depositing at least two semiconductor chips on a wafer level, and enhance an electric conductive performance by reducing an electric signal transmission path. CONSTITUTION: A lower insulating layer(40,41) is deposited on a surface of two semiconductor chips, so that a bonding pad is exposed. A metal pattern(31,32) connected to a bonding pad(11,21) is deposited on a lower insulating layer. An upper insulating layer(43,44) is deposited on a total structure. Semiconductor chip surfaces are connected to be faced therebetween. A rear surface of the upper semiconductor chip is polished and thus a predetermined thickness is removed. Outer part of the upper semiconductor chip is locally removed to form a groove. The other terminal of a metal pattern of the upper and lower semiconductor chips is exposed through the groove. Metal patterns of the exposed upper/lower semiconductor chips are interconnected by a metal connection layer(33) deposited on an inner wall of the groove. A pattern film(60) is attached on a rear surface of the upper semiconductor chip. As to the pattern film, a metal line is arranged in an insulating layer, one end of the metal line is exposed through a side surface of the insulating layer. The other terminal of the pattern film is exposed through a surface of the insulating layer, and forms a ball land. The pattern film includes a metal wire(64) for connecting one end of the metal line to the metal connection layer. A solder ball is mounted to the ball land of the pattern film. Thereby, an electric conductive performance is improved by reducing a signal transmission path, and a width of package is identical with a width of a semiconductor chip.
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