| 摘要 |
PURPOSE: A wafer level package and a method for making the same are provided to increase a deposition area of a metal pattern by depositing a metal pattern in an embossed groove, and increase a junction intensity of a solder ball by increasing a contact area between a solder ball and a metal pattern. CONSTITUTION: A wafer level package includes a semiconductor chip having the many bonding pads(11), a lower insulating layer(30), a metal pattern(40), an upper insulating layer(50), and a solder ball(60). The lower insulating layer is deposited on a bonding pad forming surface of the semiconductor chip, has a via hole exposing the bonding pad, and an embossed groove is formed to a part separated from the via hole. The metal pattern is deposited on a lower insulating layer and electrically connects the bonding pad to the embossed groove. The upper insulating layer is deposited on an upper part of a total structure, and forms a ball land exposing a metal pattern deposited on the embossed groove. The solder ball is mounted to the ball land, and is electrically connected to a metal pattern deposited on the embossed groove. |
