| 摘要 |
PROBLEM TO BE SOLVED: To improve timing margin and to reduce power consumption by automatically performing bit line recovery operation only by the control of a write driver. SOLUTION: The SRAM being this device has a memory cell array 1, a write driver 3 transferring write data to a pair of bit lines BL, bBL and supplying high level voltage for recovering a potential to the pair of bit lines BL, bBL being made a low level after write, a sense amplifier 2 for detecting and amplifying the data read out to the pair of bit lines BL, bBL, and a current source load 4. The current source load 4 is composed of PMOS transistors QP1, QP2 provided between the pair of bit lines BL, bBL and a power terminal VCC, and an inverter 14 controlling them by an inversion potential of the pair of bit lines BL, bBL.
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