| 摘要 |
PROBLEM TO BE SOLVED: To readily enable endurance test for jitting of a system clock by adding a jitter value to program clock reference(PCR) with a changer. SOLUTION: A select signal is outputted to a selector 35 at a timing outputted by a FIFO 31 of the PCR by decision circuit 32. At this time, the PCR from the FIFO 31, revolution time for the number of revolution of a revolution time part 33 and the jitter value from the switch SW are added together and outputted by an adder 36. The output of the FIFO 31 and output of the adder 36 are selected and are outputted, based on the select signal of the decision circuit 32 by the selector 35. The output of the adder 36 is selected, when the select signal is outputted and the output of the FIFO 31 is selected, when the select signal is not outputted by the selector 35. Thus, TS is outputted. Since the jitter value is added to the PCR by the changer 3, the endurance test for the system clock of the jitter is easily performed. |
