发明名称 POWER CONSUMPTION COMPUTING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT, POWER CONSUMPTION COMPUTING METHOD, AND INFORMATION STORAGE MEDIUM
摘要 PROBLEM TO BE SOLVED: To provide a power consumption computing system and a power consumption computing method thereof, capable of computing power consumption with high accuracy in consideration of effects of power consumption by glitch signals. SOLUTION: This system is provided with a power consumption computing means 20. The power consumption computing means 20 is equipped with a glitch signal detecting means 27 for detecting whether glitch signals are generated or not, a supposed load capacity computing means 28 for computing a supposed load capacity introduced to estimate an incomplete amount of electricity charged/discharged by glitch signals when the glitch signal detecting means 27 detects the glitch signals, a glitch-signal power consumption computing means 29 for computing power consumption of respective logical elements for each glitch signal by using the supposed load capacity computed by the supposed load capacity computing means 28, and a non-glitch-signal power consumption computing means 30 for computing power consumption of the respective logical elements not owing to glitch signals when no glitch signal is detected by the glitch signal detecting means 27. Power consumption by the whole of a semiconductor integrated circuit can be computed in consideration of incomplete charge/discharge by glitch signals.
申请公布号 JP2001004675(A) 申请公布日期 2001.01.12
申请号 JP19990180622 申请日期 1999.06.25
申请人 NEC CORP 发明人 TAKENAKA SHINTARO
分类号 H01L21/82;G01R21/00;G06F17/50;(IPC1-7):G01R21/00 主分类号 H01L21/82
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