发明名称 DATA CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make preventable a circuit with an FIFO function from being put into a data empty state by outputting a status signal obtained by comparing the value of a specific bit of a register indicating the number of pieces of stored data with the value of a previously set specific bit. SOLUTION: When data are already written to the circuit 5 with FIFO function, a write pointer 52 of the circuit 5 is increased by the number of the pieces of written data and when data are read out of the circuit 5, a read pointer 55 of the circuit 5 is increased by the number of the pieces of read data. At this time, the number of pieces of data stored in the circuit 5 is obtained by subtracting the read pointer 55 from the write pointer 53. The circuit 5 compares the number of the pieces of data stored in the circuit 5 with a previously set value to assert a status signal. The comparison is made by using the specific bit of the register. The status signal is connected to a DMA controller or interruption controller and serves as a DMA request or interruption request.
申请公布号 JP2001005637(A) 申请公布日期 2001.01.12
申请号 JP19990175158 申请日期 1999.06.22
申请人 MITSUBISHI ELECTRIC CORP 发明人 SATO MASAYUKI;HATA MASAYUKI
分类号 G06F13/38;G06F5/06;G06F5/14;(IPC1-7):G06F5/06 主分类号 G06F13/38
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