发明名称 LEAD TERMINAL STRUCTURE OF WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To easily recognize dislocation between a lead terminal and the bump of a semiconductor chip. SOLUTION: A dummy terminal 7 is so formed as to correspond to a non- used bump 6 on a substrate. The dimension of the dummy terminal 7 in parallel direction is equal to that of the non-used bump 6 in parallel direction. At least one of both end positions of the dummy terminal 7 in orthogonal direction and those of the non-used bump 6 in orthogonal direction as well as the tip end position of the dummy terminal 7 in parallel direction and one end position of the non-used bump 6 in parallel direction is at the same position.
申请公布号 JP2001007272(A) 申请公布日期 2001.01.12
申请号 JP19990175331 申请日期 1999.06.22
申请人 OPTREX CORP;HIROSHIMA OPT KK 发明人 MIYOSHI KATSUYA;KANETANI KENJI
分类号 G09F9/30;G02F1/1345;H01L23/50;(IPC1-7):H01L23/50 主分类号 G09F9/30
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