| 摘要 |
PROBLEM TO BE SOLVED: To enable signal timing adjustment after arrangement wiring readily, without greatly affecting a wiring between cells by constituting a plurality of dummy cells by using each set of a plurality of adjacent wiring layers prepared through combination without overlapping each other. SOLUTION: First dummy cells 11 to 18 and second dummy cells 21 to 25 are arranged alternately along each of a first diagonal line 3 and a second diagonal line 4 of a chip 1. Thereby, even in a first wiring layer and a second wiring layer in a part where second dummy cells 12 to 25 are arranged, a wiring region which can be used for wiring between cells for realizing logical function can be ensured excepting a contact hole part for connection with a transistor constituting the second dummy cells 21 to 25. Furthermore, pressure of a wiring region between cells can be relaxed, compared to an arrangement of the first dummy cells 11 to 18 in all the dummy cell positions. Therefore, signal timing adjustment can be performed readily.
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