TESTING RAMBUS MEMORIES

摘要

A RAMBUS dynamic random access memory (40) includes a test control circuit (44) that selectively couples a row address latch to either a row sense control signal or a CAD control signal. In a normal operating mode, the test control circuit couples the row address latch (26) to the row sense control signal so that the row sense control signal both latches a row address and senses a row of memory cells corresponding to the latched address. Prior to conducting a core noise test, the test control circuit couples the row address latch to the CAD control signal so that the row address is latched by the CAD control signal, and the row sense control signal only functions during the core noise test to sense a row corresponding to the latched row. The memory also includes a multiplexer (48) that receives a time-multiplexed data/address bus and simultaneously couples a first part of the data/address bus to an internal data bus and a second part of the data/address bus to an internal address bus.