DIGITAL SIGNAL PROCESSOR

摘要

A reservation processing register (26) having a construction capable of being set from an arithmetic unit (11) and storing addresses and an execution mode just as a task list (18), and a clear circuit (27) for clearing an execution mode when the address of the reservation processing register (26) is copied onto a program counter (21) are added into an arithmetic unit (12) anew. Whereby, a digital signal processor consisting of two arithmetic units may use respective arithmetic units to eliminate processing wait times and change processing sequences.