| 摘要 |
<p>There is disclosed a circuit topology for avoiding transistor gate oxide- dielectric breakdown and hot-carrier degradation in circuits, such as CMOS inverters, fabricated in a standard sub-micron CMOS process with feature size below 0.8 νm and gate-oxide thickness less than 150 Å. An inverter circuit according to the invention incorporates transistors M6, M2, M3, M5 appropriately biased, additional to those of a standard inverter circuit (comprising M1 and M4), in order to avoid hot-carrier degradation and gate-oxide breakdown of M4 and M1. The invention is also applicable to transistor circuits having other functionalities for example logic level translators.</p> |
