| 摘要 |
<p>The invention concerns a method for reconfiguring an array of parallel functional elements fault-tolerant towards said functional elements comprising said basic functional elements (P), additional functional elements (Sp), elements interconnecting (Cm) said functional elements and a control unit, said method consisting in: a step for placing the functional elements of the logic network on the physical network; a routing step which consists in programming the interconnecting elements on the physical network, selecting a maximum number of interconnecting elements capable of being run through by two neighbouring processors using a shortest path algorithm.</p> |
