VITERBI DECODER

摘要

A scalable Viterbi decoder comprises a transition metrics calculation unit (22), an add-compare-select unit (24), a survivor memory unit (28), a path metrics memory (26), and a path metrics memory address generator. The add-compare-select unit (24) comprises at least two add-compare-select devices each add-compare-select device being arranged for processing at least two trellis butterflies in at least two subsequent sub-cycles. The path metrics memory (26) comprises individually addressable memory cells, the size of each cell being such that a number of path metrics can be stored in one cell, the number of path metrics stored in one cell being equal to the number of add-compare-select devices. The path metrics memory address generator is arranged for generating write addresses which are identical to the read addresses, and for generating read addresses for the subsequent cycle by left-rotating the bits of read addresses of the preceding cycle. The add-compare-select unit further comprises an output stage for combining survivor path metrics output by the plurality of add-compare-select devices such that each memory cell receives one path metrics of each add-compare-select device per sub-cycle, and that one memory cell receives the path metrics required for the processing of one trellis butterfly. The scalable Viterbi decoder architecture allows the deployment of area-efficient and power-efficient random access memories with scalable address and data width. Adaption to different data rates becomes easily feasible.