发明名称 |
High-speed synchronous multiplexing apparatus |
摘要 |
A high-speed sprchronous multiplexing apparatus has a low-speed device and a high-speed device and employs electrical signals to interface the devices with each other. The low-speed device is connected to a low-speed digital circuit. The high-speed device is connected to a high-speed synchronous multiplexing circuit. The apparatus also has a clock supplier for supplying a reference clock signal that defines a communication rate, to each of the low- and high-speed devices. The apparatus further has an alarm processor for separating faults in the low- and high-speed devices. The low- and high-speed devices are interfaced with each other with the use of the reference clock signal and electrical STM-0/STS-1 signals that employ a frame signal synchronized with the reference clock signal. <IMAGE> |
申请公布号 |
EP0813319(A3) |
申请公布日期 |
2001.01.10 |
申请号 |
EP19970109665 |
申请日期 |
1997.06.13 |
申请人 |
FUJITSU LIMITED |
发明人 |
YAMATO, SEIICHI;KAMEI, NOBORU;OKUMA, KAZUYOSHI;SUGAWA, KATSUMI;KADOTA, HIRONORI;SAKATA, TOMOYUKI |
分类号 |
H04J3/00;H04J3/04;H04J3/06;H04J3/14;H04J3/16;H04Q11/04 |
主分类号 |
H04J3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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