CLOCK MONITOR CIRCUIT AND SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE USING THE SAME

摘要

PURPOSE: A clock monitor circuit and a synchronous semiconductor memory device using the same are provided to monitor the presence of a clock signal regardless of a period of a clock signal. CONSTITUTION: A clock monitor circuit is formed with a plurality of delay and pulse generation circuits(10,20) and an OR gate(30). The delay and pulse generation circuits(10,20) are used for receiving a clock signal(XCK) and an inverse clock signal(XCKB) from the outside, delaying the received clock signal(XCK) and the received inverse clock signal(XCKB), and generating a pulse. The OR gate(30) is used for performing a logical operation for the output signals of the delay and pulse generation circuits(10,20) and generating a stop clock signal(SCK). The delay and pulse generation circuits(10,20) are formed with a delay circuit, a NOR gate, and an inverter.