| 摘要 |
<p>A flash compatible EEPROM device has a first flash matrix and a second matrix with EEPROM functionalities of substantially similar layout, both are divided into blocks of cells formed in substrate regions isolated from one another. In said second matrix, the information is organized in pages each one contained in a row of memory cells of one of said block of subdivision of the matrix. A hierarchic structure including a row decoder addresses the wordline of all the cells of a selected row of the block, co-operating with a column decoder in selecting single cells of the rows. A boosted voltage of polarity opposite to the single supply voltage of the device is applied during an erasing phase to a single wordline selected by means of said row decoder, to page-erase said information by applying a boosted voltage to the common source of all the cells of the block and to the isolated region of the substrate containing all the cells of the block. A logical circuit confirms the programmed state of each cell containing a logic zero information of the not erased rows of the block after one or more rows or pages have been erased, applying said first boosted voltage to a wordline at a time and said supply voltage to one or more bitlines at a time for confirming a preexistent programmed state, while keeping to ground voltage the common source of all the cells of the block and the confined isolated region of the substrate. <IMAGE></p> |
