CMOS compatible SOI process

摘要

The process involves using a Silicon-On-Insulator or SOI wafer substrate with an upper substrate layer (26) for forming the CMOS components (34-40), a lateral insulation layer (24) beneath it and bearer layer (22) beneath that. The thickness of the upper layer is less than or equal to the maximum trench depth and the upper layer contains vertical insulation layers (28) down to the lateral insulation layer with components formed in the intermediate regions : An independent claim is also included for an IC with CMOS components.