发明名称 |
PLL synthesizer |
摘要 |
The operating method has a programmable frequency divider (12) inserted in a feedback loop of the phase-locked-loop synthesizer circuit used for determining the output frequency. The programmable frequency divider is operated at a different division value when the phase-locked loop synthesizer circuit is switched from a reception operating mode into a different operating mode, for providing a lower oscillation time constant for the phase- locked-loop synthesizer circuit. |
申请公布号 |
EP1067693(A1) |
申请公布日期 |
2001.01.10 |
申请号 |
EP20000113819 |
申请日期 |
2000.06.29 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
STEPP, RICHARD;KROEBEL, HANS-EBERHARD |
分类号 |
H03L7/183;H03L7/089;H03L7/093;H03L7/095;H03L7/107;H03L7/18;H03L7/197 |
主分类号 |
H03L7/183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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