发明名称 |
INTEGRATED CIRCUIT ARCHITECTURE HAVING AN ARRAY OF TEST CELLS PROVIDING FULL CONTROLLABILITY FOR AUTOMATIC CIRCUIT VERIFICATION |
摘要 |
A new circuit architecture is provided for testing digital integrated circuits which allows one to arbitrarily force any combination of logic values to be simultaneously driven onto any combination of internal nets. This allows all of the connections to each internal logic cell, and the logic cell itself, to be verified by applying a set of test patterns to each logic cell individually. In this way, the integrity of the entire device can be verified without having knowledge of the operation of the circuit as a whole. |
申请公布号 |
EP1066565(A1) |
申请公布日期 |
2001.01.10 |
申请号 |
EP19980913386 |
申请日期 |
1998.04.02 |
申请人 |
LIGHTSPEED SEMICONDUCTORS CORPORATION |
发明人 |
OSANN, ROBERT, JR. |
分类号 |
G01R31/28;G01R31/3185;G06F11/22;G06F11/267;(IPC1-7):G06F11/267 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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