| 摘要 |
PURPOSE:To improve the resolution of output frequency and also to prevent a large change of a synchronizing range by deciding a dividing number based on the output of a filter and the output of a period counter. CONSTITUTION:A phase locked loop circuit is provided with a period counter 9 which counts the continuous discriminating window signals DIS with no reference input RE, and a gate circuit 6 which supplies the filter output SD of a phase error SC and the output SH of the counter 9 and transmits the dividing number of output frequency. That is, the counter 9 recognizes a period that includes no input RE and the circuit 6 which decide the dividing number of output frequency and compensates the output SD in response to period length to decide a dividing number. Under such conditions, the resolution of the output frequency can be improved when the data transfer period is approximate to the free-running period of a dividing period 8. Meanwhile a synchronizing range is not reduced so much despite a small period of the input RE when the data transfer period is apart from the free-running period of the period 8. |
