发明名称 |
Selectable single ended-to differential output adjustment scheme |
摘要 |
A circuit comprising an input circuit and an adjustable delay. The input circuit may be configured to generate a differential signal in response to a single ended signal. The adjustable delay may be configured (i) delay or not change a rising edge or (ii) delay or not change a falling edge of a first portion of the differential signal. A second adjustable delay may be configured (i) delay or not change a rising edge or (ii) delay or not change a falling edge of a second portion of the differential signal. The differential signal may be presented to an output buffer in a Universal Serial Bus device. The present invention may also include a squaring circuit that may be configured to improve the differential alignment between the first and second portions of the differential signal.
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申请公布号 |
US6172542(B1) |
申请公布日期 |
2001.01.09 |
申请号 |
US19980192715 |
申请日期 |
1998.11.16 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
WILLIAMS TIMOTHY J.;SNYDER WARREN S. |
分类号 |
H03K5/00;H03K5/151;(IPC1-7):H03H11/16;H03H11/26 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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