发明名称 Bus-hold circuit having a defined state during set-up of an in-system programmable device
摘要 A method of operating a pin of an in-system programmable logic device (ISPLD) which includes the steps of (1) applying a predetermined voltage to the pin when the ISPLD is in a set-up mode, and (2) maintaining the last voltage applied to the pin when the ISPLD is in a normal operating mode. The ISPLD is in the set-up mode when the logic of the ISPLD has not yet been configured, or is being configured. The ISPLD is in the normal operating mode after the logic of the ISPLD has been configured. A particular ISPLD includes a pin and a logic gate having a first input terminal coupled to the pin, a second input terminal coupled to receive a control signal, and an output terminal coupled to the pin. When the ISPLD is in the set-up mode, the control signal causes the logic gate to apply a predetermined voltage to the pin. When the ISPLD is in the normal operating mode, the control signal causes the logic gate to maintain the last applied voltage on the pin.
申请公布号 US6172519(B1) 申请公布日期 2001.01.09
申请号 US19970993596 申请日期 1997.12.18
申请人 XILINX, INC. 发明人 CHIANG DAVID;JENKINS, IV JESSE H.;OLAH ROBERT A.
分类号 H03K19/173;H03K19/177;(IPC1-7):H03K19/173 主分类号 H03K19/173
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