发明名称 Redundant form address decoder for memory system
摘要 The present invention provides a memory system that retrieves data based upon redundant form address data. The memory system includes a memory having a plurality of memory lines and an address decoder that enables one of the memory lines in response to a redundant form address signal. A redundant form decoder decodes redundant form data into a differential pair of decoded address lines for each bit position of a memory address. One of the two differential pairs carries correct address data. The one address line to be used is determined on a memory line by memory line basis, using the address of the memory lines themselves. The redundant form address decoder avoids a completion add that would otherwise be required, yielding very fast access to memory.
申请公布号 US6172933(B1) 申请公布日期 2001.01.09
申请号 US19980148314 申请日期 1998.09.04
申请人 INTEL CORPORATION 发明人 SAGER DAVID J.
分类号 G11C8/00;(IPC1-7):G11C8/00 主分类号 G11C8/00
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