| 摘要 |
A circuit includes a drive transistor or selectively coupling an output terminal to a power supply. The transistor has a control terminal coupled to an input terminal by a slew rate control device to control the slew rate of the drive transistor. In an embodiment, the slew rate control device includes two parallel pass gates which implement a variable resistance for switching between a normal and a slow slew mode. In one embodiment, a tri-state output buffer is disclosed including a pull-up device and a pull-down device, each with associated pass gates for implementing slew rate control. In a favorable embodiment, a control circuit controls the pass gates so that in the slow slew mode, the drive transistors turn off as quickly as in the normal slew mode.
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