发明名称 |
Semiconductor interconnection structure and method |
摘要 |
A memory device and method in which the capacitor lower electrode within the memory cell array and a first interconnection layer within the peripheral circuitry are provided simultaneously from the same conductive material. The capacitor upper electrode and a second interconnection layer within the peripheral circuitry are also provided simultaneously from the same conductive material. |
申请公布号 |
US6172387(B1) |
申请公布日期 |
2001.01.09 |
申请号 |
US19980071860 |
申请日期 |
1998.05.04 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
THAKUR RANDHIR P. S.;WU JEFF |
分类号 |
H01L21/02;H01L21/768;H01L21/8239;H01L21/8242;H01L27/108;(IPC1-7):H01L29/78;H01L33/00 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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