发明名称 Model for simulating tree structured vlsi interconnect
摘要 Transfer functions are calculated in the following manner within an RLC tree having a input and a plurality of nodes. The RLC tree is divided into left and right sub-trees joined by the node closest to the input. Each of the left and right sub-trees is divided into left and right sub-trees joined by a node. The sub-trees are divided recursively into still smaller sub-trees until the RLC tree is completely decomposed into left and right sub-trees joined by nodes. At each node of the RLC tree, the numerator and denominator of the transfer function at that node are determined in accordance with the left and right sub-trees joined by that node. The denominator of the transfer function of the node closest to the input is taken to be the denominator of all of the transfer functions of the RLC tree. For each node, the numerators of the transfer functions of the left and right sub-trees joined at that node are corrected in accordance with the denominators of the transfer functions of the left and right sub-trees joined at that node.
申请公布号 AU5617800(A) 申请公布日期 2001.01.09
申请号 AU20000056178 申请日期 2000.06.16
申请人 UNIVERSITY OF ROCHESTER 发明人 YEHEA ISMAIL;EBY G. FRIEDMAN
分类号 G06F17/50 主分类号 G06F17/50
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