发明名称 |
DRAM cell arrangement and method for the manufacture thereof |
摘要 |
An element that prevents the formation of a channel is arranged in a level of the channel region (Kaa) at one of two opposite sidewalls of a semiconductor structure that has a source/drain region (S/D1a) and a channel region (Kaa) of a vertical selection transistor arranged therebelow. The source/drain region as well as a respective word line (W1a) adjoin at both sidewalls. For folded bit lines (B1a), respectively two word lines (W1a) can be formed in the trenches (G2a). The elements of semiconductor structures neighboring along one of the trenches (G2a) are then arranged in alternation at a sidewall of the trench (G2a) and at a sidewall of a neighboring trench (D2a). A storage capacitor can be arranged over a substrate (1a) or can be buried in the substrate (1a). The connection of the selection transistor to a bit line (B1a) can ensue in many ways.
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申请公布号 |
US6172391(B1) |
申请公布日期 |
2001.01.09 |
申请号 |
US19980140972 |
申请日期 |
1998.08.27 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
GOEBEL BERND;BERTAGNOLLI EMMERICH;KLOSE HELMUT |
分类号 |
H01L21/762;H01L21/8242;H01L27/108;H01L29/423;(IPC1-7):H01L29/78;H01L29/92 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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