| 摘要 |
A method and apparatus for levelizing transfer delays for a channel of devices. One method described determines a controller delay value by iteratively testing memory transfers to determine a largest transfer latency value using a subset of all available delays for at least one of a plurality of memory devices. Additionally, a memory device delay value for each of the plurality of memory devices is determined by testing memory transfers using at least one delay value for each of the plurality of memory devices.
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