Method of minimizing power use in programmable logic devices,申请号US09/360111-传众专利搜索

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发明名称	Method of minimizing power use in programmable logic devices
摘要
申请公布号	US6172518(B2)	申请公布日期	2001.01.09
申请号	US09/360111	申请日期	1999.07.23
申请人		发明人
分类号		主分类号
代理机构		代理人
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