| 摘要 |
PURPOSE: An adder for public key encryption at high speed is provided to improve the speed of the adder in order to perform the multiplying operation quickly in a public key encryption processor. CONSTITUTION: An OR and AND part(21) receives the data from the parts(10-15). A part(21) performs a logic NOR operation of the inputs from parts(16,12). A NOR part(25) receives the inputs from the parts(21,22). A NOR part(26) receives the data from an inverter(24) and a NOR part(19). A carry output part(27) performs a logic NAND of the inputs from the parts(25,26). A NOR part(48) receives the inputs from the parts(31,32). A NOR part(49) receives the inputs from the parts(33,34). A NOR part(54) receives the inputs from an inverter and a part(35). A NOR part(55) receives the inputs from the parts(36,37). A NOR part(57) receives the inputs from the parts(48,49,54,55). A NOR part(59) receives the inputs from the parts(50-52,53). A NOR part(58) receives the inputs from the parts(45,46,56). A carry output part(60) performs the NAND operation of the inputs from the parts(57,58,59). A NOR part(87) receives the inputs from the parts(85,86).
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