METHOD FOR IMPROVING A SIGNAL DELAY IN A FIELD PROGRAMMABLE GATE ARRAY

摘要

PURPOSE: A method for improving a signal delay in a field programmable gate array is provided by minimizing switch devices. CONSTITUTION: A field programmable gate array includes a plurality of logic blocks, wiring tracks formed widthwise and lengthwise between the logic blocks, and switch devices formed at places where the wiring tracks meet pins of the logic blocks. To improve a signal delay, a wiring format between the logic blocks is classified into subnet units as a dual pin net connecting two pins. Next, a judgement is successively made whether the subnet units can be unified or not. Some subnet units capable of unification are then subjected to the adjustment of track positions for the same value of the track. Subsequently, track positions of the other subnet units are adjusted. By doing so, unnecessary switch devices are eliminated and therefore the number of the switch devices is minimized.