| 摘要 |
<p>A circuit includes first and second pull-up transistors (301, 302) having first and second drains, respectively, each coupled to separate voltage clamps (310, 311). The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor (305), the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor (305) is coupled to the first drain via at least one pull-down transistor (303, 363, 304, 364) ) in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor (305) in series with the shared pull-down transistor (303, 363, 304, 364). This circuit may be found useful in multiplexing applications.</p> |
