发明名称 |
PROCESS FOR DESIGNING A MASK |
摘要 |
Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).
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申请公布号 |
WO0101469(A2) |
申请公布日期 |
2001.01.04 |
申请号 |
WO2000US14293 |
申请日期 |
2000.05.24 |
申请人 |
MOTOROLA INC. |
发明人 |
TRAVIS, EDWARD, O.;DENGI, AYKUT;CHHEDA, SEJAL;YU, TAT-KWAN;ROBERTON, MARK, S.;TIAN, RUIQI |
分类号 |
H01L23/52;G03F1/08;H01L21/3105;H01L21/3205;H01L21/321;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):H01L21/310 |
主分类号 |
H01L23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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